Novas' Debussy to Debug Hitachi's System LSI Designs
Debug System Increases Verification Efficiency
SAN JOSE, Calif.--(BUSINESS WIRE)--Oct. 29, 2001--Novas Software,
Inc., the leader in debug systems for complex chip designs, today
announced that Hitachi, Ltd. (NYSE:HIT - news) has signed a purchase
agreement for multiple licenses of its Debussy® debug system.
Hitachi will now take advantage of Debussy to help boost design
verification cycles of its system LSI designs.
"Prior to this recent agreement, Hitachi utilized Debussy on a
number of designs and experienced significant productivity
improvements. We will integrate this useful Debussy into SOCplanner,
our design environment and manufacturing solution for system LSIs,"
said Yoshio Okamura, department manager, Design Technology Development
Department, Design Technology Development Division, Semiconductor and
Integrated Circuits, Hitachi, Ltd. "As we continue to introduce more
advanced system LSI chips in order that our customers can downsize and
improve the performance of their end products, we must ensure our
devices are defect free. Debussy helps our engineers to quickly
locate, isolate, and understand the causes of unexpected design
behavior, which in turn significantly contributes to our success in
the marketplace."
Hitachi is producing a breadth of LSI chips integrated into
digital consumer products, car information systems, microprocessors,
and mobile networks. The size and complexity of these chips mean that
more human effort is required to verify the design. The Debussy debug
system helps to improve engineering team productivity because it
allows each engineer to understand complex design behavior faster, so
bugs can be resolved with less time and effort.
"Hitachi's decision to use Debussy on its LSI chip designs is a
testament to the ability of our technology to address the requirements
of today's most sophisticated design teams," said Scott Sandler,
president and CEO of Novas Software, Inc. "Beyond this most recent
agreement, we look forward to working with Hitachi as we introduce new
solutions that further enhance design and verification productivity in
the coming months."
About Hitachi's SOCplanner
SOCplanner is Hitachi's total system LSI platform for flexible
customer solutions with the following features: (1) system development
environment, which realizes hardware-software concurrent development
and validation environment introducing co-design and co-simulation,
(2) LSI design environment with precise one-pass design flow halving
design period, (3) silicon technology implementing high-speed,
high-integration, and low-power consumption, and (4) Hitachi core
competent SuperH(TM)/H8 cores, IPs, OSs, and middleware common to
these.
About Novas
Novas Software, Inc. focuses on improving the human understanding
process involved in debugging IC and system-on-chip (SoC) designs. The
company's technology and products provide designers with the ability
to shorten verification and debug cycles -- the most labor-intensive
and expensive portions of the design process. With its Debussy®,
Verilog and VHDL debug system, designers can easily locate, isolate,
and understand the causes of unexpected design behavior in half the
time of traditional solutions, thereby maximizing the efficiency of
engineering resources, significantly reducing costs and accelerating
the process of getting silicon to market. Novas has over 7,000 systems
in use at hundreds of customer sites worldwide. For more information
visit www.novas.com or send email to info@novas.com.
Note to Editors: Debussy and Novas are registered trademarks of
Novas Software, Inc. SuperH is a trademark of Hitachi, Ltd. All other
trademarks or registered trademarks are the property of their
respective owners.
Contact:
Novas Software
Lorie Bowlby, 408/467-7871
lorie@novas.com
Johnson Teng (Asia Headquarters)
jteng@novas.com
or
KJ Communications
Eileen Elam, 650/917-1488
